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general description the max6901 3-wire serial interface real-time clock in a sot23 package contains a real-time clock/calendar and 31 x 8 bits of static ram (sram). the real-time clock/calendar provides seconds, minutes, hours, day, date, month, year, and century information. a time/date-programmable polled alarm is included in the max6901. the end of the month date is automati- cally adjusted for months with fewer than 31 days, including corrections for leap year up to the year 2100. the clock operates in either the 24hr or 12hr format with an am/pm indicator. a push-pull 32khz output is also included. the max6901 operates with a supply voltage of +2v to +5.5v, is available in the ultra-small 8- pin sot23 package, and works over the industrial tem- perature range, -40? to +85?. applications point-of-sale equipment intelligent instruments fax machines battery-powered products portable instruments features real-time clock counts seconds, minutes, hours, day of week, date of month, month, year, and century leap-year compensation valid up to year 2100 wide +2v to +5.5v operating voltage range 3-wire serial interface, 2mhz at 5v, 500khz at 2v 31 x 8-bit sram for scratchpad data storage uses standard 32.768khz, 12.5pf watch crystal low timekeeping current (400na at 2v) single-byte or multiple-byte (burst mode) data transfer for read or write of clock registers or sram 8-pin sot23 surface-mount package push-pull 32.768khz clock output programmable time/date polled alarm function no external crystal bias resistors or capacitors required max6901 3-wire serial real-time clock in a sot23 ________________________________________________________________ maxim integrated products 1 19-2085; rev 0; 7/01 ordering information part temp. range pin- package top mark max6901eka-t -40 c to +85 c 8 sot23-8 aais related real-time clock products part serial interface alarm (bits) alarm function output frequency pin-package max6900 i 2 c compatible 31 x 8 6-sot23 max6901 3 wire 31 x 8 polled 32khz 8-sot23 max6902 spi compatible 31 x 8 polled 8-sot23 pin configuration appears at end of data sheet. functional diagram appears at end of data sheet. c 0.1 f 32.768khz crystal 1 4 3 6 2 5 3.3v 3.3v max6901 7 8 p1.0 clkin p1.1 p1.2 sclk cs i/o 32khz gnd v cc x1 x2 typical operating circuit for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. i 2 c is a trademark of philips corp. spi is a trademark of motorola, inc.
max6901 3-wire serial real-time clock in a sot23 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd....................................................... -0.3v to +6v all other pins to gnd ................................-0.3v to (vcc + 0.3v) current into any pin..........................................................20ma rate-of-rise, v cc ............................................................100v/s continuous power dissipation (t a = +70 c) 8-pin sot23 (derate 8.9mw/ c above +70 c)............714mw junction temperature .....................................................+150 c storage temperature range .............................-65 c to +150 c esd protection (all pins, human body model) ..................2000v lead temperature (soldering, 10s) .................................+300 c dc electrical characteristics (v cc = +2.0v to +5.5v, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) (note 1) parameter symbol conditions min typ max units operating voltage range v cc 2 5.5 v v cc = +2.0v 0 c < t a < +70 c 110 active supply current (note 2) i cc v cc = +5v 0 c < t a < +70 c 800 a v cc = +2.0v 0.4 0.7 timekeeping supply current (note 3) i tk v cc = +5v 1.3 1.7 a 32khz output v cc = +2.0v, i source = -0.4ma 1.8 output high voltage (note 5) v oh v cc = +5.0v, i source = -1ma 4.5 v v cc = +2.0v, i sink = 1.5ma 0.4 output low voltage (note 5) v ol v cc = +5.0v, i sink = 4ma 0.4 v duty cycle 40 % output leakage current v in = 0 to v cc , 32khz output disabled -10 10 na 3-wire digital inputs and outputs (sclk, i/o, cs) v cc = +2.0v 1.4 input high voltage v ih v cc = +5.0v 2.2 v v cc = +2.0v 0.6 input low voltage v il v cc = +5.0v 0.8 v input leakage current v in = 0 to v cc -10 10 na sclk, rst capacitance 5pf i/o capacitance 10 pf v cc = +2.0v, i sink = 1.5ma 0.4 i/o output low voltage v ol v cc = +5.0v, i sink = 4ma 0.4 v v cc = +2.0v, i source = -0.4ma 1.8 i/o output high voltage v oh v cc = +5.0v, i source = -1ma 4.5 v
max6901 3-wire serial real-time clock in a sot23 _______________________________________________________________________________________ 3 note 1: all parameters are 100% tested at t a = +25 c. limits over temperature are guaranteed by design and not production tested. note 2: i cc is specified with the i/o grounded, cs high, sclk = 2mhz at v cc = +5v; sclk = 500khz at v cc = +2.0v, 32khz output enabled, and no load on 32khz output. note 3: timekeeping current is specified with cs = gnd, sclk = gnd, i/o = gnd, 32khz = gnd, and 32khz disabled. note 4: all values referred to v ih min and v il max levels. note 5: guaranteed by design. not production tested. ac electrical characteristics (v cc = +2.0v to +5.5v, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) (figures 4, 5 and notes 1, 4) parameter symbol conditions min typ max units oscillator x1 to ground capacitance (note 5) 25 pf x2 to ground capacitance (note 5) 25 pf 3-wire serial timing v cc = +2v 200 data to clk setup t dc v cc = +5v 50 ns v cc = +2v 280 clk to data hold t cdh v cc = +5v 70 ns v cc = +2v 800 clk to data delay t cdd c l = 50pf v cc = +5v 200 ns v cc = +2v 1000 clk low time t cl v cc = +5v 250 ns v cc = +2v 1000 clk high time t ch v cc = +5v 250 ns v cc = +2v dc 0.5 clk frequency f clk v cc = +5v dc 2.0 mhz v cc = +2v 2000 clk rise and fall time t r , t f v cc = +5v 500 ns v cc = +2v 4 cs to clk setup t cc v cc = +5v 1 s v cc = +2v 240 clk to cs hold t cch v cc = +5v 60 ns v cc = +2v 4 cs inactive time t cwh v cc = +5v 1 s v cc = +2v 0 280 cs to i/o high z t cdz r l = 1k ? , c l = 60pf v cc = +5v 0 70 ns v cc = +2v 0 280 sclk to i/o high z t ccz r l = 1k ? , c l = 60pf v cc = +5v 0 70 ns
max6901 detailed description the max6901 is a real-time clock/calendar with a 3-wire serial interface and 31 ? 8 bits of sram. it provides sec- onds, minutes, hours, day of the week, date of the month, month, and year information, held in seven 8-bit timekeeping registers ( functional diagram ). an on-chip 32.768khz oscillator circuit does not require any exter- nal resistors or capacitors to operate. table 1 specifies the parameters for the external crystal, and figure 1 shows a functional schematic of the oscillator circuit. the max6901 s register addresses and definitions are described in tables 2 and 3. time and calendar data are stored in the registers in binary coded decimal (bcd) format. a polled alarm function is included for scheduled timing of user-defined times or intervals. command and control address/command byte each data transfer into or out of the max6901 is initiat- ed by an address/command byte. the address/ command byte specifies which registers are to be accessed, and if the access is a read or a write. table 2 shows the address/command bytes and their associ- ated registers, and table 3 lists the hex codes for all read and write operations. the address/command bytes are input lsb (bit 0) first. bit 0 specifies a write (logic 0) or read (logic 1). bits 1 to 5 specify the desig- nated register to be written or read. bit 6 specifies reg- ister data (logic 0), or ram data (logic 1). the msb (bit 3-wire serial real-time clock in a sot23 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25 c, unless otherwise noted.) 0.1 2.0 2.5 3.5 4.0 5.5 4.5 5.0 3.0 timekeeping current vs. supply voltage 1.0 10.0 max6901 toc01 supply voltage (v) supply current ( a) pin name function 1 sclk serial clock input. 3-wire serial clock for i/o data transfers. 2v cc power-supply pin. bypass v cc to gnd with a 0.1f capacitor. 3 x2 external 32.768khz crystal connection 4 x1 external 32.768khz crystal connection 5 32khz buffered push-pull 32.768khz output. when enabled, 32khz puts a buffered version of the timekeeping clock. when disabled, 32khz is high impedance. the power-on reset (por) default state of 32khz is enabled. 6 gnd ground connection 7 cs chip-select input. active-high for valid data transfers. 8 i/o data input/output. 3-wire serial data input/output connection. pin description
7) must be logic 1. if the msb is a zero, writes to the max6901 are disabled. clock burst mode accessing the clock burst register specifies burst- mode operation. in this mode, multiple bytes are read or written with a single address/command write. if the clock burst register is accessed (beh for write and bfh for read), the first seven clock/calendar registers (seconds, minutes, hours, date, month, day, and year) and the control register, are consecutively read or writ- ten, starting with the lsb of the seconds register. when writing to the clock registers in burst mode, all seven registers must be written in order for the data to be transferred (see example: setting the clock with a burst write ). ram burst mode sending the ram burst address/command specifies burst-mode operation. in this mode, the 31 ram regis- ters can be consecutively read or written, starting with bit 0 of address c0h for writes, and c1h for reads. burst read outputs all 31 registers of ram. when writ- ing to ram in burst mode, it is not necessary to write all 31 bytes for the data to transfer; each complete byte written is transferred to ram. when reading from ram, data bits are output until all 31 bytes have been read, or until cs is driven low. setting the clock writing to the timekeeping registers the time and date are set by writing to the timekeep- ing registers (seconds, minutes, hours, date, month, day, year, and century). during a write operation, an input buffer accepts the new time data while the time- keeping registers continue to increment normally, based on the crystal counter. the buffer also keeps the timekeeping registers from changing as the result of an incomplete write operation, and collision detection cir- cuitry ensures that a time write does not occur coinci- dent with a seconds register increment. the updated time data are loaded into the timekeeping registers on the falling edge of cs, at the end of the 3-wire serial write operation. an incomplete write operation aborts the update procedure, and the contents of the input buffer are discarded. the timekeeping registers reflect the new time, beginning with the first seconds register increment after the falling edge of cs. although both single writes and burst writes are possi- ble, the best way to write to the timekeeping registers is with a burst write. with a burst write, main timekeeping registers (seconds, minutes, hours, date, month, day, year), and the control register are written sequentially following the address/command byte. they must be written as a group of eight registers, with 8 bits each, for proper execution of the burst write function. all seven timekeeping registers are simultaneously loaded into the clock counters by the falling edge of cs, at the end of the 3-wire serial write operation. for a normal burst data transfer, the worst-case error that can occur between the actual time and the written time update is 1 second. if single write operations are used to enter data into the timekeeping registers, error checking is required. if the seconds register is not to be written, then begin by reading the seconds register and save it as initial-sec- onds. write to the required timekeeping registers and max6901 3-wire serial real-time clock in a sot23 _______________________________________________________________________________________ 5 figure 1. oscillator circuit schematic rf rd cd 25pf cg 25pf external crystal x1 x2 max6901 parameter symbol min typ max units frequency f 32.76 khz equivalent series resistance (esr) r s 40 60 k ? parallel load capacitance c l 11.2 12.5 13.7 pf q factor q 40,000 60,000 table 1. acceptable quartz crystal parameters
max6901 then read the seconds register again (final-seconds). check to see that final-seconds is equal to initial-sec- onds. if not, repeat the write process. if the seconds register is to be written, update the seconds register first, and then read it back and store its value (initial- seconds). update the remaining timekeeping registers and then read the seconds register again (final-sec- 3-wire serial real-time clock in a sot23 6 _______________________________________________________________________________________ table 2. register address/definition register address register definition function a7 a6 a5 a4 a3 a2 a1 a0 value d7 d6 d5 d4 d3 d2 d1 d0 timekeeping 00-59 32khz en 10 sec 1 sec second 1000 000 rd /w *por state 0 0 0 0 0000 00-59 alm out 10 min 1 min minute 1000 001 rd /w *por state 0 0000000 00-23 12/24 10 hr hour 1000 010 rd /w 01-12 1/0 0 a/p 0/1 10 hr 1 hr *por state 0 0 0 00000 01-28/29 01-30 01-31 0 0 10 date 1 date date 1000 011 rd /w *por state 0 0 000001 01-12 0 0 0 10m 1 month month 1000 100 rd /w *por state 0 0 0 00001 01-07 0 0 0 0 0 weekday day 1000 101 rd /w *por state 0 0 0 0 0 00 1 00-99 10 year 1 year year 1000 110 rd /w *por state 0 1 1 1 0 0 0 0 wp 0 0 0 0 0 0 0 control 1000 111 rd /w *por state 0 0 0 0 0 0 0 0 00-99 1000 year 100 year century 1001 001 rd /w *por state 0 0 0 1 1 0 0 1 note: *por state defines power-on reset state of register content.
max6901 3-wire serial real-time clock in a sot23 _______________________________________________________________________________________ 7 table 2. register address/definition (continued) register address register definition function a7 a6 a5 a4 a3 a2 a1 a0 value d7 d6 d5 d4 d3 d2 d1 d0 0 year day month date hour minute second alarm config 1001 010 rd /w *por state 0 0 0 0 0 0 0 0 reserved 0 0 0 0 0 1 1 1 do not write to this location. 1001 011 rd /w *por state 00000111 alarm thresholds 00-59 0 10 sec 1 sec second 1001 100 rd /w *por state 0 1 1 1 1111 00-59 0 10 min 1 min minute 1001 101 rd /w *por state 0 1111111 00-23 12/24 10 hr hour 1001 110 rd /w 01-12 1/0 0 a/p 0/1 10 hr 1 hr *por state 1 0 1 11111 01-28/29 01-30 01-31 0 0 10 date 1 date date 1001 111 rd /w *por state 0 0 111111 01-12 0 0 0 10 m 1 month month 1010 000 rd /w *por state 0 0 0 11111 01-07 0 0 0 0 0 weekday day 1010 001 rd /w *por state 0 0 0 0 0 11 1 00-99 10 year 1 year year 1010 010 rd /w *por state 1 1 1 1 1111 clock burst 1011 111 rd /w note: *por state defines power-on reset state of register content.
max6901 onds). check to see that final-seconds is equal to ini- tial-seconds. if not, repeat the write process. am/pm and 12hr/24hr mode bit 7 of the hours register selects 12hr or 24hr mode. when high, 12hr mode is selected. in 12hr mode, bit 5 is the am/pm bit, logic high for pm. in 24hr mode, bit 5 is the second 10hr bit, logic high for hours 20 through 23. write-protect bit bit 7 of the control register is the write-protect bit. when high, the write-protect bit prevents write opera- tions to all registers except itself. after initial settings are written to the timekeeping registers, set the write- protect bit to logic 1 to prevent erroneous data from entering the registers during power glitches or inter- rupted serial transfers. the lower 7 bits (bits 0 6) are unusable, and always read zero. any data written to bits 0 6 are ignored. bit 7 must be set to zero before a single byte write to the clock, before a write to ram, or during a burst write to the clock. example: setting the clock with a burst write to set the clock with a burst write operation to 10:11:31pm, thursday july 4th, 2002, write beh as address/command byte, followed by 8 bytes, b1h, 11h, b0h, 04h, 07h, 04h, 02h, and 00h (table 2). beh accesses the clock burst write register. the first byte, b1h, sets the seconds register to 31, and disables the 32.768khz output. the second byte, 11h, sets the minutes register to 11. the third byte, b0h, sets the hours register to 12hr mode, and 10pm. the fourth byte, 04h, sets the date register (day of the month) to the 4th. the fifth byte, 07h, sets the month register to july. the sixth byte, 04h, sets the day register (day of the week) to thursday. the seventh byte, 02h, sets the year register to 02. the eighth byte, 00h, clears the write-protect bit of the control register to allow writing to the max6901. the century register is not accessed with a burst write and therefore must be written to sep- arately to set the century to 20. note the century regis- ter corresponds to the thousand and hundred digits of the current year and defaults to 19. reading the clock reading the timekeeping registers the main timekeeping registers (seconds, minutes, hours, date, month, day, year) can be read with either single reads or a burst read. in the max6901, a latch buffers each clock counter s data. clock counter data are latched by the 3-wire serial read command (on the falling edge of sclk, after the address/command byte has been sent by the master to read a timekeeping reg- ister). collision-detection circuitry ensures that this does not happen coincident with a seconds counter 3-wire serial real-time clock in a sot23 8 _______________________________________________________________________________________ table 2. register address/definition (continued) register address register definition function a7 a6 a5 a4 a3 a2 a1 a0 value d7 d6 d5 d4 d3 d2 d1 d0 ram ram 0 1100 000 rd /w ram data 0 xxxxxxxx ram 30 1111 110 rd /w ram data 30 xxxxxxxx ram burst 1111 111 rd /w note: *por state defines power-on reset state of register content.
max6901 3-wire serial real-time clock in a sot23 _______________________________________________________________________________________ 9 write address/command byte (hex) read address/command byte (hex) description por contents (hex) 80 81 seconds 00 82 83 minutes 00 84 85 hour 00 86 87 date 01 88 89 month 01 8a 8b day 01 8c 8d year 70 8e 8f control 00 90 91 reserved nonapplicable 92 93 century 19 94 95 alarm configuration 00 96 97 reserved 07 98 99 seconds alarm threshold 7f 9a 9b minutes alarm threshold 7f 9c 9d hours alarm threshold bf 9e 9f date alarm threshold 3f a0 a1 month alarm threshold 1f a2 a3 day alarm threshold 07 a4 a5 year alarm threshold ff be bf clock burst nonapplicable c0 c1 ram 0 indeterminate c2 c3 ram 1 indeterminate c4 c5 ram 2 indeterminate c6 c7 ram 3 indeterminate c8 c9 ram 4 indeterminate ca cb ram 5 indeterminate cc cd ram 6 indeterminate ce cf ram 7 indeterminate d0 d1 ram 8 indeterminate d2 d3 ram 9 indeterminate d4 d5 ram 10 indeterminate d6 d7 ram 11 indeterminate d8 d9 ram 12 indeterminate da db ram 13 indeterminate dc dd ram 14 indeterminate de df ram 15 indeterminate e0 e1 ram 16 indeterminate e2 e3 ram 17 indeterminate table 3. hex register address/description
max6901 increment to ensure accurate time data is being read. the clock counters continue to count and keep accu- rate time during the read operation. the simplest way to read the timekeeping registers is to use a burst read. in a burst read, the main timekeep- ing registers (seconds, minutes, hours, date, month, day, year) and the control register are read sequential- ly in the order listed with the seconds register first. they are read out as a group of eight registers, with 8 bits each. all timekeeping registers (except century) are latched upon the receipt of the burst read com- mand. the worst-case error between the actual time and the read time is 1 second for a normal data transfer. the timekeeping registers may also be read using single reads. if single reads are used, it is necessary to do some error checking on the receiving end, because it is possible that the clock counters could change during the read operations, and report inaccu- rate time data. the potential for error is when the seconds register increments before all the registers are read. for example, suppose a carry of 13:59:59 to 14:00:00 occurs during single read operations. the net data read could be 14:59:59, which is erroneous. to prevent errors from occurring with single read oper- ations, read the seconds register first (initial-seconds) and store this value for future comparison. after the remaining timekeeping registers have been read, reread the seconds register (final-seconds). check that the final-seconds value equals the initial-seconds value; if not, repeat the entire single read process. using single reads at a 100khz serial speed, it takes under 2.5ms to read all seven of the timekeeping registers, including two reads of the seconds register. example: reading the clock with a burst read to read the time with a burst read, send bfh as the address/command byte. then clock out 8 bytes, seconds, minutes, hours, date of the month, month, day of the week, year, and finally the control byte. all data are output lsb first. decode the required informa- tion based on the register definitions listed in table 2. using the alarm a polled alarm function is available by reading the alm out bit. the alm out bit is d7 of the minutes time- keeping register. a logic 1 in alm out indicates the alarm function is triggered. there are eight registers associated with the alarm function, seven programma- ble alarm threshold registers and one programmable alarm configuration register. the alarm configuration register determines which alarm threshold registers are compared to the timekeeping registers, and the alm out bit sets if the compared registers are equal. table 2 shows the function of each bit of the alarm configuration register. placing a logic 1 in any given bit of the alarm configuration register enables the respec- tive alarm function. for example, if the alarm 3-wire serial real-time clock in a sot23 10 ______________________________________________________________________________________ write address/command byte (hex) read address/command byte (hex) description por contents (hex) e4 e5 ram 18 indeterminate e6 e7 ram 19 indeterminate e8 e9 ram 20 indeterminate ea eb ram 21 indeterminate ec ed ram 22 indeterminate ee ef ram 23 indeterminate f0 f1 ram 24 indeterminate f2 f3 ram 25 indeterminate f4 f5 ram 26 indeterminate f6 f7 ram 27 indeterminate f8 f9 ram 28 indeterminate fa fb ram 29 indeterminate fc fd ram 30 indeterminate fe ff ram burst nonapplicable table 3. hex register address/description (continued)
configuration register is set to 0000 0011, alm out is set when both the minutes and seconds indicated in the alarm threshold registers match the respective timekeeping registers. once set, alm out stays high until it is cleared by reading or writing to the alarm configuration register, or by reading or writing to any of the alarm threshold registers. the alarm configuration register is written with address/command 94h, and read with address/command 95h. using the on-board ram the static ram is 31 x 8 bits addressed consecutively in the ram address space. even-addressed com- mands (c0h fch) are used for writes, and odd- addressed commands (c1h fdh) are used for reads. the contents of the ram are static and remain valid for v cc down to 2v. all ram data are lost if power is cycled. the write-protect bit (bit 7 of the control regis- ter), when high, disallows any changes to ram. 3-wire serial interface interfacing the max6901 with a microcontroller is accomplished by using a 3-wire, synchronous, serial interface. required to communicate are a chip select signal (cs), a serial clock signal (sclk), and a data line (i/o). all data transfers are framed by the cs signal that must be active-high for any data transfer to occur. at the beginning of any data transfer (rising edge of cs), sclk should be low. this prevents the max6901 from misinterpreting the transition of cs as a high-to-low transition of sclk (if sclk were to be left high when cs transitions from a low to high). the first 8 bits sent after cs is pulled high by the microcontroller comprise the address/command byte, which tells the max6901 if the data transfer is a read or a write, and which regis- ter is read to or written from. data are clocked into the max6901, through the i/o pin, on the rising edges of sclk, and data are clocked out on the falling edge of sclk. data format is always lsb first to msb last. when cs is low, i/o is high impedance. single data transfer timing is shown in figure 2. burst- mode data transfer timing is shown in figure 3. detailed read and write timing diagrams are shown in figures 4 and 5, respectively. chip select cs serves two functions. first, cs turns on the control logic that allows access to the shift register for address/command and data transfer. second, cs pro- vides a method of terminating either single-byte or mul- tiple-byte data transfers. all data transfers are initiated by driving cs high. if cs is low, i/o is high impedance. at power-up, cs must be low until v cc 2.0v. serial clock a clock cycle on sclk is a rising edge followed by a falling edge. for data input, data must be valid at i/o during the rising edge of the clock. for data outputs, bits are valid on i/o after the falling edge of clock. also, sclk must be low when cs is driven high. data input (single-byte write) following the eight sclk cycles that input a single- byte write address/command, data bits are input on the rising edges of the next eight sclk cycles. additional sclk cycles are ignored. input data lsb first. data input (burst write) following the eight sclk cycles that input a burst write address/command, data bits are input on the rising edges of the following sclk cycles. the number of clock cycles depends on whether the timekeeping reg- isters or ram are being written. a clock burst write requires an address/command byte, 7 timekeeping data bytes, and 1 control register byte. a burst write to ram may be terminated after any complete data byte by driving cs low. input data lsb first (figures 3 and 5). data output (single-byte read and burst read) a read from the max6901 is initiated by an address/ command write from the microcontroller (master) to the max6901 (slave). the address/command write portion of the data transfer is clocked into the max6901 on ris- ing clock edges. on the eighth rising sclk edge, the last bit of the address/command byte is clocked into the max6901. after t cdh (clk to data hold time, figure 4), the microcontroller must release the data line. on the eighth falling edge of sclk, the max6901 takes control of the data line and begins to output data. the max6901 outputs data on the falling edge of sclk after t cdd (clk to data delay time, figure 4). on the next rising edge of sclk, i/o goes to high impedance after t ccz (which is specified with a maximum time). minimum time for t ccz can be 0ns. since the i/o line can go to high impedance on the rising edge of sclk, it is best to read the data from the max6901 before the rising edge of sclk but after t cdd (clk to data delay time). this is best accomplished through the microcon- troller i/o port pins by writing a low to sclk, waiting t cdd (clk to data delay time), reading the max6901 i/o pin, and then writing a high to sclk. data bytes are output lsb first. additional sclk cycles transmit addi- tional data bits, as long as cs remains high. this per- mits continuous burst-mode read capability. max6901 3-wire serial real-time clock in a sot23 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max6901 32.768khz output (32khz) 32khz is a push-pull 32.768khz output for timing or clocking of external devices. bit d7 in the clock seconds register is the active-low enable bit for 32khz. when d7 is logic 0, 32khz is enabled. when logic 1, 32khz is disabled and set to high impedance. power- on reset enables the 32.768khz output. applications information crystal selection the max6901 is designed to use a standard 32.768khz watch crystal. table 1 details the recommended crystal requirements. some suggested crystals are listed in table 4. in addition to the specified smt devices, some of the listed manufacturers also offer other package options. frequency stability and temperature timekeeping accuracy of the max6901 is dependent on the frequency stability of the external crystal. to determine frequency stability, use the parabolic curve in figure 6 and the following equations: ? f = fk (t 0 - t) 2 where: ? f = change in frequency from +25 c 3-wire serial real-time clock in a sot23 12 ______________________________________________________________________________________ figure 2. single byte data transfer sclk a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 cs i/o address/command byte i/o data byte 11 a1 a2 a3 a4 a5 r r = ram/ register select bit ram = 1, register = 0 address/command byte (b) 3-wire single byte write: (a) 3-wire single byte read: i/o data byte a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 cs sclk i/o d7 0 a1 a2 a3 a4 a5 r 1 r = ram/ register select bit ram = 1, register = 0
f = nominal crystal frequency k = parabolic curvature constant (-0.035ppm/ c2 0.005ppm/ c2 for 32.768khz watch crystals) t 0 = turnover temperature (+25 c 5 c for 32.768khz watch crystals) t = temperature of interest ( c) for example: what is the worst-case change in oscilla- tor frequency from +25 c ambient to +45 c ambient? ? f drift = 32,768 ? (-0.04 ? (1 ? 10 -6 )) ? (20-45) 2 = -0.8192hz what is the worst-case timekeeping error per second? error due to temperature drift: ? t drift = {[1 / [(f+ ? f drift ) / 32768]]-1s} / 1s ? t drift = {[1 / [(32768 - 0.8192) / 32768]]-1}/1s = 0.000025s/s error due to +25 c initial crystal tolerance of 20ppm: ? f initial = 32,768 ? (-20 ? ((1 ? 10 -6 )) = -0.65536hz ? t initial = {[1 / [(f+ ? f initial ) / 32768]]-1s} / 1s ? t initial = {[1 / [(32768-0.65536) / 32768]]-1} / 1s = 0.000025s/s total timekeeping error per second: max6901 3-wire serial real-time clock in a sot23 ______________________________________________________________________________________ 13 figure 3. burst mode data transfer a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 cs sclk i/o address/command byte i/o data byte 1 d0 d1 d2 d3 d4 d5 d6 d7 i/o data byte n r 11 1 111 1 n = 8 for timekeeping register burst n = 31 max for ram burst a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 cs sclk i/o d7 d0 d1 d2 d3 d4 d5 d6 d7 0111 11r1 r = ram/ register select bit ram = 1, register = 0 r = ram/ register select bit ram = 1, register = 0 address/command byte i/o data byte 1 i/o data byte n n = 8 for timekeeping register burst n = 31 max for ram burst (b) 3-wire burst write: ()
max6901 ? t total = ? t drift + ? t initial ? t total = 0.00002+0.000025=0.000045s/s after 1 month, that translates to: total worst-case timekeeping error at the end of 1 month at +45 c is about 120s or 2 min (assumes negli- gible parasitic layout capacitance). oscillator start time the max6901 oscillator typically takes 5s to 10s to begin oscillating. to ensure the oscillator is operating correctly, the software should validate proper time- keeping. this is accomplished by reading the seconds register. any reading of 1s or more from the por value of zero is a validation of proper startup. power-on reset the max6901 contains an integral por circuit that ensures all registers are reset to a known state on power-up. once v cc rises above 1.6v (typ), the por circuit releases the registers for normal operation. when ? t days hr day hr s ss s = () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () = 31 24 60 60 0 00045 120 528 min min ./. 3-wire serial real-time clock in a sot23 14 ______________________________________________________________________________________ figure 4. 3-wire read data transfer serial timing diagram 01701 cs sclk i/o t cc t dc t cdd t cdz t cdd t ccz t cdh read address/command byte read data bit figure 5. 3-wire write data transfer serial timing diagram cs sclk i/o t cc t dc t cdh t cwh t cl t cdh write address/command byte write data bit t r t f t cch 017 0
v cc drops to less than 1.6v (typ), the max6901 resets all register contents to the por defaults (table 2). reserved registers addresses/commands 90h, 91h, 96h, and 97h are reserved for factory testing only. do not write to these registers. if inadvertent writes are done to any of these registers, cycle power to the max6901. power-supply considerations for most applications, a 0.1f capacitor from v cc to gnd provides adequate bypassing for the max6901. a series resistor can be added to the supply line for oper- ation in extremely harsh or noisy environments. timekeeping current?ormal operation when i/o is high impedance (cs = low, or after each rising-clock edge for a data output transfer), there is a potential for increased timekeeping current (up to 100x) if the i/o is allowed to float. if minimum timekeeping current is desired, the microcontroller port pin should be configured as an input with a weak pullup. alternatively, use a 100k ? or less pulldown or pullup resistor (for microcontroller port pins with 1a input leakage). there are similar considerations for 32khz if it is placed in its high-impedance state. for lowest time- keeping current, it should not be allowed to float. force it high or low, or terminate it with a pullup or pulldown resistor. timekeeping current?attery backup systems often times, an rtc is operated in a system with a backup battery. a microprocessor supervisory circuit with backup battery switchover, or other switching arrangement, is used to switch power from v cc to v batt when v cc falls below a set threshold. most of these systems leave only the rtc and some sram to run from v batt . the microcontroller that communicates with the rtc is powered only from v cc . when the microcontroller is reset, its port pins typically become high impedance. this essentially floats i/o, cs, and sclk on the max6901. there is a potential for increased timekeeping current (up to x100) as v cc falls through the linear region of the input gates for i/o, sclk, and cs. the duration of this effect depends on the discharge rate of v cc . to minimize current draw from v batt in such systems, ensure that v cc falls rapidly at power down. one option is a v cc discharge resistor of 100k ? or less from v cc to ground. this also ensures sufficient impedance when v cc is gone back through the microcontroller s esd protection, to keep i/o, sclk, and cs from floating. alternately, a 100k ? pulldown (for microcontroller port pins with 1a input leakage) on each pin (i/o, sclk, and cs) ensures that timekeeping current specifications are met during the power switchover. max6901 3-wire serial real-time clock in a sot23 ______________________________________________________________________________________ 15 table 4. 32.768khz surface-mount watch crystals manufacturer manufacturer part no. temp. range c l (pf) +25 c frequency tolerance (ppm) abracon corporation abs25-32.768-12.5-b-2-t -40 c to +85 c 12.5 20 caliber electronics aws2a-32.768khz, -20 c to +70 c 12.5 20 ecs inc international ecs-.327-12.5-17 -10 c to +60 c 12.5 20 fox electronics fsm327 -40 c to +85 c 12.5 20 m-tron sx2010/ sx2020 -20 c to +75 c 12.5 20 raltron rse-32.768-12.5-c-t -10 c to +60 c 12.5 20 saronix 32s12a -40 c to +85 c 12.5 20 figure 6. typical temperature curve for 32.768khz watch crystal typical temperature characterisitics (k = 0.035ppm/ c 2 , t o = +25 c) ? f (ppm) temperature ( c) -250 -200 -150 -100 -50 0 -50 -40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90
max6901 there are similar considerations for 32khz if it is placed in its high-impedance state. for lowest time- keeping current, it should not be allowed to float. force it high or low, or terminate it with a pullup or pulldown resistor. pc board layout considerations the max6901 uses a very-low-current oscillator to mini- mize supply current. this causes the oscillator pins, x1 and x2, to be relatively high impedance. exercise care to prevent unwanted noise pickup. connect the 32.768khz crystal directly across x1 and x2 of the max6901. to eliminate unwanted noise pick- up, design the pc board using these guidelines (figure 7): place the crystal as close to x1 and x2 as possible and keep the trace lengths short; place a guard ring around the crystal, x1 and x2 traces (where applica- ble), and connect the guard ring to gnd; keep all sig- nal traces away from beneath the crystal, x1, and x2. finally, an additional local ground plane can be added under the crystal on an adjacent pc board layer. the plane should be isolated from the regular pc board ground plane, and tied to ground at the max6901 ground pin. restrict the plane to be no larger than the perimeter of the guard ring. do not allow this ground plane to contribute significant capacitance between x1 and x2. chip information transistor count: 26,214 process: cmos 3-wire serial real-time clock in a sot23 16 ______________________________________________________________________________________ figure 7. printed circuit board layout for crystal connections sm watch crystal 0.1 f sm cap * * * * * * ** * * * layer 1 trace * ** ** ground plane via connection guard ring ground plane via connection ground plane via connection v cc plane via connection ** ** layer 2 local ground plane connect only to pin 6 ground plane via max6901
max6901 3-wire serial real-time clock in a sot23 ______________________________________________________________________________________ 17 oscillator 32.768khz divider 31 8 ram address register input shift registers control logic 1hz x1 x2 v cc gnd sclk i/o 32khz alarm control logic alarm out cs seconds minutes hours date month day year control century alarm configuration test configuration alarm thresholds clock burst ram burst functional diagram gnd 32khz x1 1 2 8 7 i/o cs v cc x2 sclk sot23 top view 3 4 6 5 max6901 pin configuration
max6901 3-wire serial real-time clock in a sot23 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information sot23, 8l.eps

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